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XMEGA A [MANUAL]
8077I–AVR–11/2012
19.3.1 I2C and SMBus Compliance
19.3.1.1 Electrical Characteristics
The TWI module in XMEGA devices follows the electrical specifications and timing of I2C bus and SMBus. These
specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus timeout period should be set
in TWI master mode. Refer to “TWI Master Operation” on page 210 for more details.
19.3.1.2 SMBus
Section 2 of the SMBus 2.0 spec states that powered-down devices must not provide a path to ground. Due to our ESD
diodes, our powered down device do provide a path to ground.
The following SMBus items need to be implemented in software:
35ms clock low timeout.
Layer 3 - Network layer.
19.3.2 START and STOP Conditions
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a transaction. The master
issues a START condition (S) by indicating a high-to-low transition on the SDA line while the SCL line is kept high. The
master completes the transaction by issuing a STOP condition (P), indicated by a low-to-high transition on the SDA line
while SCL line is kept high.
Figure 19-3. START and STOP conditions.
Multiple START conditions can be issued during a single transaction. A START condition that is not directly following a
STOP condition is called a repeated START condition (Sr).
19.3.3 Bit Transfer
As illustrated by Figure 19-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line.
Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the
TWI module.
Figure 19-4. Data validity.
Combining bit transfers results in the formation of address and data packets. These packets consist of eight data bits
(one byte) with the most-significant bit transferred first, plus a single-bit not-acknowledge (NACK) or acknowledge (ACK)
SDA
SCL
START
Condition
STOP
Condition
S
P
SDA
SCL
DATA
Valid
Change
Allowed
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